The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for internal bypassing of memory array devices.
As will be appreciated by those skilled in the art, in a domino Static Random Access Memory (SRAM), the individual cells do not employ sense amplifiers to sense the differential voltage on the bit line pairs coupled to the cross-coupled inverters that store the data. Rather, for a domino SRAM, the local bit line is precharged, discharged, and the discharge is detected. The local bit line, the means to precharge the local bit line, and the detector define a dynamic node of the domino SRAM.
In a high-speed domino memory array, the array access time may vary widely, depending upon the strength of the cell device that discharges the bit line. As the wafer dimensions of these narrow devices continue to decrease, the process induced variations in fabrication continue to increase. In addition, when the array is written, the access time associated with the data driver switching the bit line can produce an even earlier effective read output of the array. Thus, an enable signal is used to control access timing to the array.
The ability to present the data being written into a memory such as an SRAM (or some logical function of the data) to the output of the memory is a feature that continues to be an issue for many applications. One approach to this problem is to write through the local bitline structure. However, as indicated above, a drawback to this write through solution is that it has become unreliable for fast, domino read style memories due to the so called “fast read before write” effect. Attempts to extend the write through solution add complexity and require additional trade offs. For example, externally bypassing the entire memory requires the addition or expansion of a series multiplexer (and possibly the addition of staging latches), which in general increases the latency and area of the memory. Since the timing of an external bypass scheme is independent of the memory, this also adds to the timing complexities of the downstream logic.